High reliability is customarily achieved in switching system designs by duplication critical elements. As an alternative to full duplication, an n+1 sparing design has been used in some switching systems in which one unit (e.g., a time-slot interchange unit or a memory unit) is designated as the spare for N associated active units. With such a design approach, the spare unit is provided with special connections to the associated units and can be controlled to temporarily perform the functions of one of the associated units. In the arrangement of U.S. Pat. No. 4,700,340 issued to A. J. Beranek et al. on Oct. 13, 1987, a plurality of identical switching circuits are provided, including a plurality of spare switching circuits, for serving subscriber terminals connected via communication lines. A logical address is stored for each active switching circuit, as well as the physical designation of all switching circuits. A data distribution operating under control of control data selectively distributes data packets from the communication lines to the active switching circuits. In the Beranek arrangement, a single control processor, which is responsible for the set of active and spare switching circuits, is responsive to change control signals identifying an active switching circuit, to store the logical address assigned to the identified active circuit in correspondence with a selected spare circuit in the memory of the single control processor, there by designating the latter circuit as active. The single processor further transfers control data to the distribution circuit to control distribution of data packets to the selected switching circuit which has been designated to be active. System programs may employ logical addresses for the switching circuits and any reassignment of the physical circuits does not require a corresponding change in system programs. Although the Beranek arrangement achieves flexibility and convenience in reconfiguring a plurality of units under the control of a single control processor, the problem is substantially more difficult when the units to be reconfigured are under the control of a plurality of distributed control entities.
U.S. Pat. No. 4,710,926 issued to D. W. Brown et al. on Dec. 1, 1987, discloses a distributed control switching system having a plurality of processor modules (referred to as processors) that are interconnected by a bus. Line processors serve corresponding user teleterminals, and call control processors are used to direct the various phases of call processing in a switching system. A message called a heartbeat is broadcast among the processors once during each major processing cycle. The heartbeat message indicates the physical and logical identity of the transmitting processor with respect to the system arrangement as well as the processor's present operational state. By monitoring the heartbeats from other processors, spare processors can autonomously take over the functions of failed processors without being required to consult or obtain the approval of an executive processor. The new physical location of a replaced processor will be automatically recorded by the other processors. The Brown arrangement provides for ready reconfigurations because there is no fixed association between call control processors and line processors. However, since the switching mechanism is based on a simple bus rather than one a network of distributed switching units, the capacity of the switching system in terms of the number of lines and trunks that can be effectively served is limited.
The AT&T switching system disclosed in the AT&T Technical Journal, July-Aug. 1985, Vol. 64, No. 6, Part Two, advantageously combines distributed control and distributed switching. The hardware architecture has three major components: an administrative module (AM), a communications module (CM), and one or more switching module (SMs). The AM provides the system-level interfaces required to operate, administer, and maintain the switching system. It performs functions that can most economically be done globally, such as common resource allocation and maintenance control. The basic function of the CM is to provide consistent communication between the SMs, and between the AM and the SMs. The CM includes a message switch which transfers call processing and administrative messages between the SMs and the AM, and between any two SMs. The CM further includes a time-multiplexed switch comprising a single-stage switching network that provides the digital paths for switched connections between the modules and for control messages among the modules. SMs provide call-processing intelligence, the first stage of switching network, and line and trunk units. The SMs represent distributed switching units. Each SM includes a switching module processor (SMP) which controls call processing, call distribution, and maintenance functions. The SMPs represent distributed control units. However, once the lines and trunks of the system are connected to SMs, there is no possibility of balancing the load between MSs. Accordingly, one SM may be taxed because of the processing requirements being placed on its SMP while another is limited because of the time-slot capacity of its time-slot interchange unit. Although the SMPs and time-slot interchange units are duplicated, the peripheral circuits (lines or trunks) served by a given SM are necessarily taken out of service upon a failure of duplicated units, even though other SMs and SMPs are fully functional and, perhaps, underloaded. Flexible reconfiguration has heretofore not been possible because the association between peripheral circuits, SMPs, and SM time-slot interchange units has been fixed.
In view of the foregoing, a need exists in the art for flexible reconfiguration of switching system functional units, particularly in systems combining distributed control and distributed switching.